Generally, in a common type of semiconductor memory device, in particular, in a DRAM (Dynamic Random Access Memory), a substrate voltage having a relatively negative electric potential is generated and is applied to a substrate of the memory chip.
FIG. 1 is a circuit diagram illustrating a conventional substrate voltage generation circuit.
In FIG. 1, the conventional substrate voltage generation circuit includes: a substrate voltage detector 10, having loads L1 and L2 (such loads including transistors), that is connected in series between a supply voltage VCC and a substrate voltage VBB, and that outputs a divided voltage via a node N1; an inverter 11 for inverting the divided output voltage from the substrate voltage detector 10 and outputting the inverted voltage via a node N2; an inverter 12 for inverting the output voltage from the inverter 11 and outputting the inverted voltage via a node N3; an oscillator 13 for oscillating in accordance with the voltage output via the node N3 from the inverter 12; and a substrate voltage generator 14, driven by the oscillation signal from the oscillator 13, for applying the substrate voltage VBB, which is used for charge pumping, and which has a predetermined electric potential to the substrate voltage detector 10.
The inverter 11 includes PMOS transistors PM1 and PM2 and an NMOS transistor NM1 which are connected in series with one another.
The inverter 12 includes a PMOS transistor PM3 and an NMOS transistor NM2 which are connected in series with one another.
The operation of the conventional substrate voltage generation circuit will now be explained with reference to FIGS. 1 and 2.
The substrate voltage detector 10 divides the voltage difference between the supply voltage V.sub.cc and the substrate voltage VBB by the ratio of the loads L1 and L2 and applies the divided voltage to the node N1.
If the voltage of the node N1 is at a high level, the inverter 11 outputs a low level signal on the node N2, and the inverter 12 inverts this signal and applies a high level signal to the oscillator 13 through the node N3. In response to the high voltage on the node N3, the oscillator 13 becomes enabled, and the oscillation signal therefrom is applied to the substrate voltage generator 14.
In response to a high voltage on the node N3, the substrate voltage generator 14 decreases the substrate voltage VBB (which is used for a charge pumping). If the substrate voltage VBB reaches a predetermined level, the divided voltage at the node N1 becomes a low level, and the low level voltage is inverted by the inverters 11 and 12 in turn and is applied as a low level voltage to the oscillator 13 through the node N3. Thereafter, the oscillation operation of the oscillator 13 is stopped by the low level voltage inputted thereinto.
In the inverter 11, the PMOS transistor PM2 (the gate of which is connected to ground so that PM2 is always turned on), acts as a resistor. So, when the PMOS transistor PM1 is turned on, the current at the node N2 is limited by the active resistor PM2.
The inverters 11 and 12 act as a buffer, so that the electric potential of the node N1 is slowly varied based on the variation of the supply voltage V.sub.cc or the substrate voltage VBB.
FIG. 2 is a graph illustrating the variation of the substrate voltage VBB in accordance with a supply voltage V.sub.cc variation in the circuit as shown in FIG. 1.
As shown therein, reference character "a" denotes a variation range of the supply voltage V.sub.cc, "b" denotes the variation range of a threshold voltage for the inverter 11, and "e" denotes an enabling time of the oscillator based on the variation of the supply voltage V.sub.cc.
Namely, in a state that the voltage V.sub.cc has a high electric potential, if the substrate voltage VBB is increased from -2v to 0v, the electric potential of the node N1 is varied as indicated by the curve N1' in FIG. 2, the electric potential of the node N3 is varied as indicated by the line N3', and the logic threshold voltage of the inverter 11 is varied as indicated by the line VT'. The electric potential of the nodes N2 and N3 are inverted at the point "A" between the line VT' of the inverter 11 and the line N3' of the node N3, for thus enabling the oscillator 13, and the substrate voltage generator 14 is driven, and the level of the substrate voltage VBB decreases to a substrate voltage VBB' corresponding to the point "A".
In addition, in a state that the voltage V.sub.cc has a low electric potential, if the substrate voltage VBB is increased from -2 v to 0 v, the electric potential of the node N1 is varied as indicated by the curve N1", and the electric potential of the node N3 is varied as indicated by the line N3", and the logic threshold voltage of the inverter 11 is varied based on the line VT". At this time, the substrate voltage generator 14 is driven at the point "B", and the level of the substrate voltage VBB decreases to the substrate voltage VBB" corresponding to the point "B".
When the voltage V.sub.cc is varied, the oscillator 13 and the substrate voltage generator 14 become activated differently thus varying the level of the resulting substrate voltage VBB. However, the variation range "e" of the substrate voltage VBB, as shown in FIG. 2, is largely and disadvantageously dependent on the voltage V.sub.cc.
The voltage VBB is used to bias the substrate for NMOS transistors. When VBB varies (.DELTA.VBB), this can cause the speed of a device employing NMOS transistors to speed up or slow down, both of which can cause the device to malfunction. Thus, it is of great importance to minimize .DELTA.VBB.
The conventional art attempted to make VBB insensitive to changes in VCC (.DELTA.VCC) by making the logic threshold Vt of the buffer (formed from the inverters 11 and 12) insensitive to .DELTA.VCC. More particularly, the conventional art made the logic threshold of the inverter 11, Vt(11), insensitive to .DELTA.VCC. This is depicted by the curve 50 of FIG. 5, which represents the relation between VCC and the logic threshold voltage of the particular embodiment of the conventional inverter 11a of FIG. 6. The inverter 11a differs from the inverter 11 by not having the active resistor PM2, and by having explicit channel dimensions and a channel dimension ratio (channel width:channel length) for each of the transistors.
The channel dimensions for the transistors of the inverter 11a of FIG. 6 are: PM1, 3 .mu.m in width, 45 .mu.m in length, for a ratio of 1:15; and NM1, 15 .mu.m in width, 3 .mu.m in length, for a ratio of 5:1. The Vt(11a) is approximately Vt (NM1). As a result, the curve 50 is very flat over the range of about 2 to 5 volts. In other words, Vt(11a) is very much insensitive to .DELTA.VCC. Unfortunately, having Vt(11a) that is insensitive to .DELTA.VCC exaggerates .DELTA.VBB.